1. Field of the Invention
The present invention relates to semiconductor circuits formed on a semiconductor chip, and more particularly, to a semiconductor circuit having a phase lock function.
2. Description of the Background Art
Recently, the operation in LSIs (Large Scale Integrated circuits) is increased in speed. However, delay in the internal clock signal of a LSI has become noticeable in accordance with the increase in speed of operation. This delay in an internal clock signal will retard the increase in speed of a LSI. To solve this delay in an internal clock signal, a PLL (Phase Locked Loop) circuit is formed on a LSI semiconductor chip. This PLL circuit carries out control such that the phase of an internal clock signal is locked to a reference value of a phase of an external clock signal so that an internal clock signal is generated in a phase identical to that of external clock signal. Also, a circuit formed on said semiconductor chip is known for detecting the locked state of the above-described PLL circuit. Such a locked detection circuit is disclosed in, for example, Japanese Patent Laying-Open Nos. 64-24630, 2-284521, 1-129614, 3-159318 and 3-206725.
FIG. 11 is a block diagram showing a structure of a conventional locked detection circuit and a PLL circuit.
The structure of a PLL circuit 10 will first be described. Referring to FIG. 11, a phase comparison circuit 2 is supplied with a reference input signal R from an input terminal 1 and a feedback signal V from a VCO (Voltage Control Oscillator) 5. Phase comparison circuit 2 compares the phase of reference input signal R with that of feedback signal V to provide an up signal U (a low level signal) and a down signal D (a high level signal) which are pulse signals having a pulse width according to the phase difference to match the phases of these signals. Up signal U is a signal to advance the phase of an output signal of VCO 5, and down signal D is a signal for delaying the phase of an output signal of VCO 5.
A charge pump 3 is formed of a PMOS transistor 33 and an NMOS transistor 34 connected in series between a power supply potential 31 receiving a power supply voltage and a ground terminals 32. In charge pump 3, an up signal U is supplied to the gate of PMOS transistor 33 from phase comparison circuit 2, and a down signal D is supplied to the gate of NMOS transistor 34 from phase comparison circuit 2. Charge pump 3 transforms the up and down signals U and D into a voltage pulse by the operation of PMOS transistor 33 and NMOS transistor 34. The voltage pulse is supplied to a loop filter 4.
Loop filter 4 integrates the voltage pulse provided from charge pump 3 to supply the same to VCO 5. VCO 5 functions to change the oscillation frequency according to the output voltage of loop filter 4. When an up signal U is provided, the oscillation frequency is raised to advance the phase of the output signal. When a down signal D is provided, the oscillation frequency is lowered to delay the phase of the output signal. The output signal of VCO 5 is provided from output terminal 6 and also fed back to phase comparator 2.
PLL circuit 10 of the above-described structure has a locked detection circuit 8 connected thereto. An up signal U or a down signal D output from phase comparator 2 is supplied to locked detection circuit 8. Locked detection circuit 8 detects the locked state of PLL circuit 10 according to the up and down signals U and D to provide the detection result.
This conventional locked detection circuit 8 had a problem that the performance evaluation of a semiconductor circuit such as a LSI including a PLL circuit could not be carried out accurately prior to shipment of that semiconductor circuit because the jitter level which prevents accurate locking of an internal clock signal could not be identified.